Evolution of FPGA Verification and How to Address Today's Verification Challenges

Overview

Since the advent of digital RTL design in the early nineties, designers have needed to verify their designs. With the increasing complexity of designs, driven by Moore’s law, achieving first pass success has become more challenging. The costs of failure in an ASIC project are obvious (respin NREs above $100k, and months of schedule slip, to name a few). The costs of failure in an FPGA project can be just as detrimental, but aren't as obvious. They include things like missing the market window because of late introduction, or issues with the product in the field (tarnishing your brand).

 

What You Will Learn

• New technologies with assertions
• Constrained randomization
• Algorithmic test bench design
• Formal verification

 

Who Should Attend

• Digital ASIC/FPGA designers
• Verification Engineers
• Project Managers

 

Products Covered

ModelSim®

 

Details

What

Web Seminar: Evolution of FPGA Verification and How to Address Today's Verification Challenges

 

When

Thursday the 22nd of March 2018

 

Where
Online

 

Register

4:30 PM CET